The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device provided with a data input driver and a data output driver for inputting and outputting data, respectively, and a driving method thereof.
In general, a semiconductor memory device, including Double Data Rate Synchronous RAM (DDR SDRAM), stores or outputs data in accordance with a command required by a Central Processing Unit (CPU). If a write command is provided from the CPU, data from the outside is stored in a memory cell corresponding to an address required by the CPU, and if a read command is provided from the CPU, data stored in a memory cell corresponding to an address required by the CPU is outputted to the outside. That is, in a write operation, input data is applied to a data input driver via a data input/output pad and then fed to a memory cell, and in a read operation, data to be outputted from a semiconductor memory device is first provided to a data output driver and then outputted to the outside via the input/output pad.
FIG. 1 is a circuit diagram illustrating a typical data input driver 110 and a data output driver 130.
Referring to FIG. 1, the data input driver 110 compares an input data signal DIN provided via an input/output pad 150 with an external reference signal VREF and buffers the comparison result to output an internal data signal DAT_INN. Here, the external reference signal VREF is a voltage which is provided from the outside and has a ½ voltage level of an external power supply voltage VDD applied to a semiconductor memory device. And, an activation signal EN is used to activate an input operation of the data input driver 110 and is activated during a write operation of the semiconductor memory device.
The data output driver 130 drives an output terminal in response to data signals DAT_PU and DAT_PD to be outputted from the semiconductor memory device, the output terminal denoting a node to which an output data signal DOUT is outputted, and outputs the output data signal DOUT to the outside via the input/output pad 150. The data output driver 130 includes a pull-up pre-drive unit 132, a pull-down pre-drive unit 134, and a main drive unit 136.
The pull-up pre-drive unit 132 generates a pull-up drive control signal CTR_PU in response to a pull-up data signal DAT_PU, and the pull-down pre-drive unit 134 generates a pull-down drive control signal CTR_PD in response to a pull-down data signal DAT_PD. Here, the pull-up data signal DAT_UP and the pull-down data signal DAT_PD indicate data signals synchronized with a clock signal generated from a delay locked loop (not shown) for example.
The main drive unit 136 pull-up or pull-down drives the output terminal in response to the pull-up drive control signal CTR_PU and the pull-down drive control signal CTR_PD. That is, the output data signal DOUT becomes logic ‘high’ in response to the pull-up drive control signal CTR_PU and becomes logic ‘low’ in response to the pull-down drive control signal CTR_PD.
FIGS. 2A, 2B, and 2C are waveform diagrams for explaining the input operation of the data input driver 110 shown in FIG. 1, in which the data input driver 110 has three waveforms as shown depending on a voltage level of an external power supply voltage VDD.
FIG. 2A shows a case where an external power supply voltage VDD has a voltage level (hereinafter, referred to as target voltage level) considered in the initial design. In this case, the external reference voltage VREF, the input data signal DIN, and the internal data signal DAT_INN shown in FIG. 1 will be referred to as VREF_M, DIN_M, and DAT_INN_M, respectively, for convenience of explanation.
Referring to FIGS. 1 and 2A, the data input driver 110 compares the input data signal DIN_M with the external reference signal VREF_M to output the internal data signal DAT_INN_M. Here, the input data signal DIN is inputted with a duty ratio of 50:50 with respect to the external reference voltage VREF. Accordingly, the internal data signal DAT_INN_M is also outputted with a duty ratio of 50:50.
FIG. 2B shows a case where the external power supply voltage VDD is lower than the target voltage level. In this case, the external reference voltage VREF, the input data signal DIN, and the internal data signal DAT_INN in FIG. 1 will be referred to as VREF_L, DIN_L, and DAT_INN_L, respectively, for convenience of explanation.
Referring to FIGS. 1 and 2B, the data input driver 110 compares the input data signal DIN_L with the external reference signal VREF_L to generate the internal data signal DAT_INN_L. At this time, the input data signal DIN_L is inputted with a voltage level between a maximum voltage level and a minimum voltage level preset with respect to the external reference voltage VREF_L. Therefore, it has a duty ratio of 50:50, as in the case of FIG. 2A.
However, since a voltage level of the external power supply voltage VDD is lower than the target voltage level to reduce a drive current of the data input driver 110, the internal data signal DAT_INN_L in FIG. 2B does not maintain a duty ratio of 50:50.
FIG. 2C represents a case where the external power supply voltage VDD is higher than the target voltage level. In this case, the external reference voltage VREF, the input data signal DIN, and the internal data signal DAT_INN in FIG. 1 will be referred to as VREF_H, DIN_H, and DAT_INN_H, respectively, for convenience of explanation.
Referring to FIGS. 1 and 2C, the data input driver 110 has an increased drive current by a higher voltage level of the external power supply voltage VDD. Therefore, the internal data signal DAT_INN_H does not maintain a duty ratio of 50:50, as in the case of FIG. 2B.
That is to say, in the cases of FIGS. 2B and 2C, the duty ratio of the internal data signal becomes not constant depending on a voltage level of the external power supply voltage VDD. This inconstant duty ratio results in a reduction in reliability of the internal data signal.
FIG. 3 shows waveforms for explaining the output operation of the data output driver 130 shown in FIG. 1.
As described in FIG. 1, the data output driver 130 is constituted by the pull-up and the pull-down pre-drive units 132 and 134, and the main drive unit 136. The pull-up and the pull-down pre-drive units 132 and 134 determine a time point the main drive unit 136 becomes on or off and also determine a slew rate of the output data signal DOUT to be outputted from the main drive unit 136 based on the determined time point.
Next, a PMOS transistor provided in the main drive unit 136 is turned on by an NMOS transistor provided in the pull-up pre-drive unit 132 and an NMOS transistor provided in the main drive unit 136 is turned on by a PMOS transistor provided in the pull-down pre-drive unit 134. Because of this, the NMOS transistor in the pull-up pre-drive unit 132 and the PMOS transistor in the pull-down pre-drive unit 134 should be designed in an appropriate size, especially by considering the slew rate.
Shown in (A), (B) and (C) of FIG. 3 are a pull-up data signal DAT_PU, a pull-down data signal DAT_PD, an output data signal DOUT_M in case of (A) of FIG. 3 where the external power supply voltage VDD has the target voltage level, an output data signal DOUT_L in case of (B) of FIG. 3 where the external power supply voltage VDD is lower than the target voltage level, and an output data signal DOUT_H in case of (C) of FIG. 3 where the external power supply voltage VDD is higher than the target voltage level.
As can be seen from the drawings, in case of (B) of FIG. 3, the external power supply voltage VDD has a lower voltage level, so that the pull-up and the pull-down pre-drive units 132 and 134 make the on/off time point of the main drive unit 136 slower. Thus, the slew rate of the output data signal DOUT_L becomes smaller. That is, a slope of the output data signal DOUT_L becomes smaller than DOUT_M in (A) of FIG. 3.
On the contrary, in case of (C) of FIG. 3, the external power supply voltage VDD has a higher voltage level, so that the on/off time point of the main drive unit 136 becomes faster. Thus, the slew rate of the output data signal DOUT_H becomes greater. That is, a slope of the output data signal DOUT_H becomes greater than DOUT_M in (A) of FIG. 3.
That is, in cases of (B) and (C) of FIG. 3, the slew rate of the output data signal varies depending on a voltage level of the external power supply voltage VDD. In general, since the slew rate of the output data signal is related to data reliability and power consumption, it is preferably designed in a manner that the slew rate should properly be maintained based on the data reliability and power consumption. However, the cases illustrated in (B) and (C) of FIG. 3 do not maintain the slew rate.
FIGS. 4A and 4B are views for explaining current characteristics in terms of the external power supply VDD of the main drive unit 130 in FIG. 1. That is, FIG. 4A represents characteristics of current being consumed by the main drive unit 130 during the pull-down operation and FIG. 4B represents characteristics of current being consumed by the main drive unit 130 during the pull-up operation. In each of the FIGS. 4A and 4B, two characteristic lines {circle around (1)} indicate the lower limit and the upper limit of current being consumed, which are defined as specification, respectively. A characteristic line {circle around (2)} denotes a case where the external power supply voltage VDD is higher than the target voltage level, and a characteristic line {circle around (3)} denotes a case where the external power supply voltage VDD has the target voltage level. A characteristic line {circle around (4)} represents a case where the external power supply voltage VDD is lower than the target voltage level.
As can be seen from FIGS. 4A and 4B, the current being consumed does not meet the specification as the voltage level of the external power supply varies.
As described above, the typical data input driver 110 and the data output driver 130 have different operational characteristics depending on a voltage level of the external power supply voltage VDD. This cannot ensure sufficient reliability in data exchange operations between the data input driver 110 and the CPU and between the data output driver 130 and the CPU.
Moreover, since the current being consumed exists outside of the range defined in the spec, mass-production and compatibility of products can be decreased. That is, if the products manufactured do not meet the spec, they are dealt with as being defective, thus lowering the efficiency of mass-production. For example, suppose that there are environments where an external supply voltage VDD of 1 V is used and an external supply voltage VDD of 1.5 V is used. In this case, if one of them does not meet the spec, compatibility may be reduced.